Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor
The continued scaling of semiconductor technologies leads to diverse challenges such as power and temperature, which also forces reliability as another design metric of prime concern. There exists strong need to link reliability with physical metrics in a high-level architecture design environment, where estimation of reliability impacts can be performed in the early design stage. In this paper, we propose a joint modeling and
simulation framework for power, thermal and timing variation, which is integrated into a commercial high-level processor design environment. A custom timing variation model is provided for estimation of dynamic timing variation, which is demonstrated using one nanoscale thermal effect known as Inverted Temperature Dependence. The complete modeling flow is automated for customized processor model with arbitrary architectural hierarchy, which assists designer to perform architectural and application-level design space exploration with power, thermal and reliability impacts.
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